This invention relates to a voltage detection circuit and an adjustable comparison voltage generator which can be used in the voltage detection circuit.
Certain types of semiconductor integrated circuits need to internally generate (i.e., within the circuit) a signal voltage which is higher than a power supply voltage. Examples of such circuits are electrically erasable and programmable read-only memory chips that need high programming or writing voltages. Such circuits require a voltage detection circuit for producing an internal reference voltage and for comparing a detected voltage with the reference voltage. The voltage detection circuit also includes means for adjusting the reference voltage.
A prior art reference voltage generator is shown in FIG. 1, which is extracted from FIG. 10, of "high-Voltage Regulation and Process Considerations for high-Density 5 V-only E.sup.2 PROM's," IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 5, October 1983, p. 536. The portion enclosed in the chain line is a reference voltage generator 1, which provides a reference voltage V.sub.N1 at a node N1. The voltage to be compared with the reference voltage V.sub.N1 is labeled V.sub.GEN. The comparison is performed by a differential amplifier I1, the output OUT of which can be used to regulate V.sub.GEN. The differential amplifier can be a device with two output states that detects when V.sub.GEN exceeds the reference voltage and furnishes an output signal OUT that is high when V.sub.GEN is greater than V.sub.N1 and low when V.sub.GEN is less than V.sub.N1. The output OUT is connected to a circuit, not shown in the drawing, that controls V.sub.GEN, such as a circuit comprising a pumping circuit that raises V.sub.GEN while OUT is low and a switching circuit that suspends the pumping action when OUT becomes high.
The reference voltage generator 1 includes a differential amplifier circuit 2 comprising load resistors R3 and R4 connected to the supply voltage Vcc, an NMOS enhancement-type transistor T3, an NMOS depletion-type transistor T4, and a constant-current source 13. One terminal of the constant-current source 13 is connected to ground; the other terminal is connected via a node N5 to the source terminals of the transistors T3 and T4; the drain terminals of the transistors T3 and T4 are respectively connected through nodes N3 and N4 to the load resistors R3 and R4. The gate terminal of the transistor T3 is connected to a node N2. The gate terminal of the transistor T4 is grounded. The gate terminals of the transistors T3 and T4 act as the inputs of the differential amplifier circuit 2.
The differential amplifier circuit 2 serves as an input stage for another differential amplifier I2, the output of which is the reference voltage V.sub.N1 provided at the node N1. The output of the differential amplifier I2 is also connected through a resistor string comprising resistors R0, R1, and R2 to the node N2, which is an input node of the differential amplifier circuit 2. Due to this circuit topology and to the threshold difference between the enhancement-type NMOS transistor T3 and the depletion-type NMOS transistor T4, the differential amplifier circuit 2 and the differential amplifier I2 form a negative feedback loop which holds the reference voltage V.sub.N1 at a constant level which may exceed the level of the supply voltage.
The resistors R0, R1, and R2, which are connected in series between the output node N1 and the internal node N2, provide a means of adjusting the reference voltage. The resistance values of the resistors R0, R1, and R2 are in the ratio 1:2:4. NMOS enhancement-type transistors T0, T1, and T2 are connected in parallel with the resistors R0, R1, and R2 respectively. The gate terminals of the transistors T0, T1, and T2 are connected to input signal lines BIT0, BIT1, and BIT2. High and low logic levels applied to the input signal lines BIT0, BIT1, and BIT2 switch the transistors T0, T1, and T2 on and off. The logic levels on the lines BIT0 to BIT2 represent binary-coded data representing the value of the reference voltage.
If the on-state resistances of the transistors T0, T1, and T2 are negligibly small in comparison to the resistances of the resistors R0, R1, and R2, then the total resistance R between the nodes N1 and N2 is the sum of the resistances of those resistors R0, R1, and R2 for which the corresponding transistor T0, T1, or T2 is turned off.
The node N2, in addition to being connected to the gate of the transistor T3, is grounded through a constant-current source I4. Let V.sub.N2 be the voltage at node N2. Then, EQU V.sub.N1 =V.sub.N2 +R.multidot.I4
Since the differential amplifier circuit 2 and differential amplifier I2 operate in a linear fashion, the reference voltage V.sub.N1 should in theory be a linear function of the digital value applied to BIT0, BIT1, and BIT2. Hence V.sub.GEN should be a linear function of this digital input value.
As FIG. 2 shows, however, V.sub.GEN is not in fact a linear function of the digital input applied to BIT0, BIT1, and BIT2. The data in FIG. 2 were derived by simulating the operation of the circuit in FIG. 1 on a computer and finding the value of V.sub.GEN that causes the output OUT of the differential amplifier I1 to invert.
When the output voltage of the voltage detection circuit is used as a control signal for a high voltage generator, the generated voltage V.sub.GEN is dependent on the power supply voltage V.sub.CC for the internal circuit. The generated voltage may be used for writing in an EEPROM. In such a case, when the power supply voltage V.sub.CC is lowered, the writing voltage V.sub.GEN is also lowered. This may cause a failure of the writing.
Moreover, the linearity of the generated voltage V.sub.GEN with respect to the reference voltage setting data of the prior art circuit is poor, so that it was difficult to minutely adjust the generated voltage V.sub.GEN.
Furthermore, it is necessary to increase the number of bits of the reference voltage setting data to achieve minute adjustment of the generated voltage. However, the resistances of the resistors R0, R1 and R2 must be larger than the on-state resistances of the transistors T0, T1 and T2. It was therefore difficult to increase the number of the bits of the reference voltage setting data.